1. Field of the Invention
The present invention relates to a method of producing a test pattern of a semiconductor device as well as a computer-readable record medium bearing a program of producing the test pattern of the semiconductor device, and in particular relates to a method of producing a test pattern of a semiconductor device which allows determination of acceptance and rejection of a semiconductor device without causing a timing problem as well as a computer-readable record medium bearing a program of producing a test pattern of a semiconductor device.
2. Description of the Background Art
If timing verification of a semiconductor device is performed with a static timing verifying tool allowing inclusive timing verification, timing for a false path which is not used during system operation is also verified so that an unnecessary timing offense is detected in some cases. In the prior art, therefore, such manners are frequently employed that the false pass is excluded, in advance, from a target of timing verification, or a timing offense is ignored, in advance. Then, a test pattern is produced with a test pattern producing tool.
However, the foregoing test pattern producing tool cannot recognize a false path, so that a test pattern using the false path, i.e., a test pattern having a possibility of causing a timing problem is produced. When a test of a semiconductor device is conducted with such a test pattern, acceptance and rejection may be erroneously determined.